View LB11823M_242078.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Ordering number : ENN7106
Monolithic Digital IC
LB11823M
Direct PWM Drive Brushless Motor Predriver for OA Products
Overview
The LB11823M is a direct PWM drive predriver IC for use with three-phase power brushless motors. The LB11823M can implement a motor drive circuit with the desired output capacity (voltage and current) by using appropriate external transistors. Due to its built-in FG amplifier and other features, this device is optimal for motor drive in OA products that use power brushless motors.
Package Dimensions
unit: mm 3129-MFP36SD
[LB11823M]
36 19
Functions and Features
* * * * * * Three-phase bipolar drive Direct PWM drive Built-in FG amplifier and Schmitt comparator circuits Braking function (short-circuit braking) Built-in forward/reverse switching circuit Full complement of built-in protection circuits, including current limiter, undervoltage protection circuit, motor lockup protection circuit, and thermal protection circuit. * Can be controlled by either a command voltage or the duty of an input PWM signal.
15.2 0.1 (2.25) 2.45max 0.65 Unit V V V mA V V V V 4 20 VCC2 14.5
1
18
0.25
0.35
0.8
(0.8)
SANYO: MFP36SD
Specifications
Absolute Maximum Ratings at Ta = 25C
Parameter Supply voltage 1 Supply voltage 2 Supply voltage 3 Output current RF pin applied voltage LVS pin applied voltage TOC pin applied voltage VCTL pin applied voltage Symbol VCC1 max VCC2 max VCC3 max IO max VRF max VLVS max VTOC max VCTL max VCC1 pin VCC2 pin VCC3 pin Pins UL, VL, WL, UH, VH, WH Conditions Ratings 14.5 14.5 20 40
Continued on next page.
Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
80102RM (OT) No. 7106-1/19
9.2 10.5
7.9
LB11823M
Continued from preceding page.
Parameter Allowable power dissipation Operating temperature Storage temperature Symbol Pd max Topr Tstg Independent IC Conditions Ratings 0.9 -20 to +100 -55 to +150 Unit W C C
Allowable Operating Range at Ta = 25C
Parameter Supply voltage range 1-1 Supply voltage range 1-2 Supply voltage range 2 Supply voltage range 3 Output curent 12V constant-voltage output current 5V constant-voltage output current HP pin applied voltage HP pin output current FGS pin applied voltage FGS pin output current Symbol VCC1-1 VCC1-2 VCC2 VCC3 IO I12REG IREG VHP IHP VFGS IFGS VCC1 pin VCC1 pin, with VCC1-VREG short-circuited VCC2 pin VCC3 pin Pins UL, VL, WL, UH, VH, WH Conditions Ratings 8 to 13.5 4.5 to 5.5 4.5 to VCC1 13.5 to 19 30 -50 -20 0 to 13.5 0 to 10 0 to 13.5 0 to 7 Unit V V V V mA mA mA V mA V mA
Electrical Characteristics at Ta = 25C, VCC1 = 12 V, VCC2 = VREG
Parameter Supply current 1 Supply current 2 Output block Output voltage 1-1 Output voltage 1-2 Output voltage Temperature coefficient 1-1 Temperature coefficient 1-2 Temperature coefficient 2 12 V Regulator-voltage output (12REG pin) Output voltage Voltage regulation Load regulation Temperature coefficient 5 V Regulator-voltage output (VREG pin) Output voltage Voltage regulation Load regulation Temperature coefficient VREG VREG1 VREG2 VREG3 VCC1 = 8 to 13.5 V IO = -5 to -20 mA Design target value* 4.7 5.0 40 5 0 5.3 100 30 V mV mV mV/C V12REG VCC3 = 15 V, IO = -30 mA 11.7 12.1 150 100 2 12.6 300 200 V mV mV mV/C 12VREG1 VCC3 = 13.5 to 19 V, IO = -30 mA 12VREG2 IO = -5 to -45 mA, VCC3 = 15 V 12VREG3 Design target value* VOUT1-1 VOUT1-2 VOUT2 Low level IO = 400 A Low level IO = 10 mA High level IO = -20 mA VCC1 - 1.1 0.1 0.8 VCC1 - 0.9 0.2 -1.5 1.5 0.3 1.1 V V V mV/C mV/C mV/C Symbol ICC1-1 ICC1-2 Stop mode Conditions Ratings min typ 15 3.5 max 21 5 Unit mA mA
VOUT1-1 Design target value*, Low level IO = 400 A VOUT1-2 Design target value*, Low level IO = 10 mA VOUT2 Design target value*, High level IO = -20 mA
Note*: These items are design target values and are not tested.
Continued on next page.
No. 7106-2/19
LB11823M
Continued from preceding page.
Parameter Hall Amplifier Block Input bias current Common-mode input voltage range 1 Common-mode input voltage range 2 Hall input sensitivity Hysteresis width Input voltage L H Input voltage H L VCTL pin Input voltage 1 Input voltage 2 Input bias current 1 Input bias current 2 PWM oscillator (PWM pin) Output H level voltage Output L level voltage External C charge current Oscillator frequency Amplitude TOC pin Input voltage 1 Input voltage 2 Input voltage 1L Input voltage 2L Input voltage 1H Input voltage 2H HP pin Output saturation voltage Output leakage current FGS pin Output saturation voltage Output leakage current FG amplifier Input offset voltage Input bias current Output H level voltage Output L level voltage FG input sensitivity VIO (FG) IB (FG) VOH (FG) IFG0 = -0.2 mA VOL (FG) IFG0 = 0.2 mA Gain 100-fold 3 -10 -1 VREG - 1.2 VREG - 0.8 0.8 1.2 10 1 mV A V V mV VFGS IO = 5 mA 0.15 0.5 10 V A VHPL IHP leak IO = 7 mA VO = 13.5 V 0.15 0.5 10 V A VTOC1 VTOC2 VTOC1L VTOC2L VTOC1H VTOC2H Output duty 0% Output duty 100% Design target value*, 0% with VCC2 = 4.7 V Design target value*, 100% with VCC2 = 4.7 V Design target value*, 0% with VCC2 = 5.3 V Design target value*, 100% with VCC2 = 5.3 V 2.72 0.99 2.72 0.99 3.08 1.11 3.0 1.2 2.80 1.08 3.20 1.22 3.30 1.34 2.90 1.17 3.30 1.34 V V V V V V VOH (PWM) VOL (PWM) ICHG f (PWM) V (PWM) VPWM = 2.1 V C = 1000pF 2.75 1.0 -60 17.6 1.6 3.0 1.2 -45 22 1.8 3.25 1.3 -30 26.8 2.1 V V A kHz Vp-p VCTL1 VCTL2 Output duty 0% Output duty 100% 1.05 3.0 -80 1.4 3.5 -60 60 80 1.75 4.1 V V A A VIN (HA) VSLH (HA) VSHL (HA) IHB (HA) VICM1 VICM2 Hall device used For input one-side bias (Hall IC application) -2 0.5 0 50 20 5 -25 30 15 -15 50 25 -5 -0.5 VCC1 - 2.0 VCC1 A V V mVp-p mV mV mV Symbol Conditions Ratings min typ max Unit
IB1 (CTL) VCTL = 0 V IB2 (CTL) VCTL = 5 V
IFGS leak VO = 13.5 V
Note*: These items are design target values and are not tested.
Continued on next page.
No. 7106-3/19
LB11823M
Continued from preceding page.
Parameter Common phase input voltage range Next-stage Schmidt width Operation frequency range Open loop GAIN CSD oscillator (CSD pin) Output H level voltage Output L level voltage External C charge current External C discharge current Oscillator frequency Amplitude Current limiter circuit (RF pin) Limiter voltage Low-voltage protection circuit (LVS pin) Operating voltage Release voltage Hysteresis width VSDL VSDH VSD TSD TSD f (PI) VIH (PI) VIL (PI) VIO (PI) VIS (PI) IIH (PI) IIL (PI) VIH (SS) VIL (SS) VIO (SS) VIS (SS) IIH (SS) IIL (SS) VIH (FR) VIL (FR) VIO (FR) VIS (FR) IIH (FR) IIL (FR) VF/R = VREG VF/R = 0 V VS/S = VREG VS/S = 0 V VPWMIN = VREG VPWMIN = 0 V 2.0 0 VREG - 0.5 0.2 -10 -130 0.3 0 -96 Design target value* (junction temperature) Design target value* (junction temperature) 3.6 4.1 0.35 3.8 4.3 0.5 4.0 4.5 0.65 V V V VRF 0.45 0.5 0.55 V VOH (CSD) VOL (CSD) ICHG1 ICHG2 f (CSD) V (CSD) C = 0.01 F 2.2 3.2 0.9 -14 7 3.6 1.1 -10 11 200 2.5 2.75 4.0 1.3 -6 15 V V A A Hz Vp-p f (FG) = 2 kHz 45 49 Symbol VICM Conditions Ratings min 1.2 40 80 typ max VREG - 2.0 140 10 Unit V mV kHz dB
Thermal shutdown operation (Overheat protection circuit) Thermal shutdown operating temperature Hysteresis width PWMIN pin Input frequency H level input voltage L level input voltage Input open voltage Hysteresis width H level input current L level input current S/S pin H level input voltage L level input voltage Input open voltage Hysteresis width H level input current L level input current F/R pin H level input voltage L level input voltage Input open voltage Hysteresis width H level input current L level input current 2.0 0 VREG - 0.5 0.2 -10 -130 0.3 0 -96 VREG 1.0 VREG 0.4 10 V V V V A A 2.0 0 VREG - 0.5 0.2 -10 -130 0.3 0 -96 VREG 1.0 VREG 0.4 10 V V V V A A 50 VREG 1.0 VREG 0.4 10 kHz V V V V A A 125 20 145 25 165 30 C C
Note*: These items are design target values and are not tested.
Continued on next page.
No. 7106-4/19
LB11823M
Continued from preceding page.
Parameter BR pin H level input voltage L level input voltage Input open voltage Hysteresis width H level input current L level input current REVSEL pin H level input voltage L level input voltage Input open voltage H level input current L level input current VIH (REVSEL) VIL (REVSEL) VIO (REVSEL) IIH (REVSEL) VREVSEL = VREG IIL (REVSEL) VREVSEL = 0 V 2.0 0 VREG - 0.5 -10 -130 0 -96 VREG 1.0 VREG 10 V V V A A VIH (BR) VIL (BR) VIO (BR) VIS (BR) IIH (BR) IIL (BR) VBR = VREG VBR = 0 V 2.0 0 VREG - 0.5 0.2 -10 -130 0.3 0 -96 VREG 1.0 VREG 0.4 10 V V V V A A Symbol Conditions Ratings min typ max Unit
Note*: These items are design target values and are not tested.
Allowable power dissipation, Pdmax - W
Pd max - Ta
1.0 0.9W 0.8 0.6 0.4 0.36W 0.2 Independent IC
-20
0
20
40
60
80
100
120
Ambient temperature, Ta - C
No. 7106-5/19
LB11823M Three-Phase logic Truth Table (IN = [H] indicates a condition in which IN+ > IN-.)
F/R = L IN1 1 2 3 4 5 6 H H H L L L IN2 L L H H H L IN3 H L L L H H IN1 L L L H H H F/R = H IN2 H H L L L H IN3 L H H H L L Output PWM VH WH WH UH UH VH -- UL UL VL VL WL WL
When the OFF mode is selected during reversing at the REVSEL pin, it is necessary to specify the Hall input condition. With F/R = "L", the condition in which the Hall input is entered in the order from 1 to 6 in the above table is considered the forward rotation and that in the reverse order is considered reversing. With F/R = "H", the condition in which the Hall input is entered in the order from 6 to 1 in the above table is considered the forward rotation and that in the reverse order is considered reversing. S/S pin
Input condition H or open L Condition Stop Start
REVSEL pin
Input condition H or open L Condition -- OFF mode for reversing
BR pin
Input condition H or open L Condition -- Brake
PWMIN pin
Input condition H or open L Condition Output OFF Output ON
When S/S and PWMIN pins are not used, set the input to the L level voltage. When REVSEL and BR pins are not used, set the input to the H level voltage or the open condition.
Pin Assignment
NC 36
NC 35
GND REVSEL BR 34 33 32
HP 31
F/R 30
PWMIN 29
S/S 28
CSD 27
VCTL 26
PWM 25
TOC 12REG VCC3 24 23 22
LVS 21
VCC2 VREG 20 19
LB11823M
1 RF 2 WH 3 WL 4 VH 5 VL 6 UH 7 UL 8 VCC1 9 IN1+ 10 IN1- 11 IN2+ 12 IN2- 13 IN3+ 14 IN3- 15 FG+ 16 17 18
FG- FGOUT FGS
No. 7106-6/19
LB11823M Pin Description
Pin No. Symbol Pin Description Equivalent circuit
VREG
Output current detection 1 RF Connect a resistor (Rf) between this pin and ground. Set with the maximum output current IOUT = 0.5/Rf.
5k
1
VCC1
2 4 6 3 5 7 WH VH UH WL VL UL Output pin (external TR drive output) Duty control made on UH, VH, and WH sides.
2 3
4 5
6 7
8
VCC1
Power supply (output and Hall input blocks). Normally used with the 12 V power supply. Connect to VCC2 and VREG for application with the 5 V single power supply. Connect a capacitor between this pin and GND for stabilization.
VCC1
9 10 11 12 13 14 IN1+ IN1- IN2+ IN2- IN3+ IN3- Hall amplifier input. IN+ > IN- is the input high state, and the reverse is the input low state. Connect a capacitor between the s IN+ and IN- inputs if there is noise in the Hall sensor signals.
300 9 11 13
300 10 12 14
VREG
15 16
FGIN+ FGIN-
FG amplifier inputs IN+ is the noninverting input. IN- is the inverting input.
15
300
300
16
Continued on next page.
No. 7106-7/19
LB11823M
Continued from preceding page.
Pin No. Symbol Pin Description Equivalent circuit
VREG
17
FG OUT
FG amplifier output pin
17
40k
FG Schmidt comparator VREG 18
18 FGS FG Schmidt output pin
VCC1
Regulated-voltage output pin (5V output) 19 VREG Connect a capacitor (about 0.1F) between this pin and ground for stabilization.
19
Power pin (PWM oscillation, PWM comparator, VCTL amp). Normally connect to VREG. 20 VCC2 In applications that apply a voltage externally to the VCTL or TOC pin and use a fixed output duty, variations in the duty can be suppressed by connecting this pin to VCC1 (12 V).
VCC1
Voltage detection pin for low-voltage protection. 21 LVS To detect the supply voltage of 5 V or more, connect the zenor diode in series to set the detection voltage.
43k
21
18k
Continued on next page.
No. 7106-8/19
LB11823M
Continued from preceding page.
Pin No. Symbol Pin Description Equivalent circuit
22
Power pin (VCC3) for use during application with the supply voltage of 12 V or more. 12 V is generated at the 12 REG pin. To use the 12REG pin, connect this pin to V CC1. When not used, keep both V CC 3 and 12 REG open or connect them to GND.
22 23
VCC3 12REG
23
VCC2
PWM waveform comparator pin. 24 TOC Normally used in the open condition. By inputting the voltage directly into this pin, the output duty can be controlled without using the VCTL amp.
24
20k
VCC2
25
PWM
Pin to set the PWM oscillation frequency. Connect a capacitor between this pin and GND.
200 2k
25
34k VCC2
26
VCTL
Control voltage input pin. For control with this pin, set the PWMIN pin to the L level.
2.26V
40k
26
VREG
Pin to set the operation time of motor lock protection circuit and to set the initial reset pulse. 27 CSD Connect a capacitor between this pin and GND. When the protection circuit is not to be used, connect a capacitor and resistor (150k, 4700pF) in parallel between this pin and GND.
300
27
Continued on next page.
No. 7106-9/19
LB11823M
Continued from preceding page.
Pin No. Symbol Pin Description Equivalent circuit
VREG
50k
28 S/S Start/stop control pin. Start with L and stop with H or in the open condition
3.5k 28
VREG
50k
PWM pulse input pin. 29 PWM IN Output drive with L and output OFF with H or in the open condition. For control with this pin, apply the voltage of VCTL2 voltage or more to the VCTL pin.
3.5k 29
VREG
50k
30 F/R Forward/reverse input pin
3.5k 30
VREG 31
31 HP Hall signal three-phase synthesis output signal
VREG
50k
32 BR Brake input pin. Brake with L and normal rotation with H or in the open condition.
3.5k 32
Continued on next page.
No. 7106-10/19
LB11823M
Continued from preceding page.
Pin No. Symbol Pin Description Equivalent circuit
VREG
50k
REV SEL Reverse OFF selector pin. Effective with L and ineffective with H or in the open condition.
3.5k 33
33
34 35 36
GND
GND pin
NC
NC pin that can be used for wiring
No. 7106-11/19
LB11823M Hall-Effect Sensor Input/Output Timing Chart
F/R = L IN1 IN2
Forward
IN3 UH VH WH UL VL WL F/R = H IN1 IN2 Forward
IN3 UH VH WH UL VL WL
PWM output
No. 7106-12/19
VREG 5V
VREG 12VREG LVS VCC2 LVSD VREG VREG VCC1 12VREG
FGIN-
FGOUT
FGS
VCC3 VM
- FG FILTER
FGIN+
-
+
VREG
+
HP
TOC
VCTL
-
+ COMP PRI LOGIC HALL LOGIC TSD DRIVER UH UL VH VL WH WL CURR BR HALL HYS REV SEL AMP LIM RF
LB11823M
Sample Application Circuit (1) Bipolar transistor drive (upper side PWM) using a 5 V power supply
PWM
PWM OSC
VREF
S/S
SD
PWM IN
OSC
F/R
S/S BR VCC1 H
PWMIN
CSD
F/R
REVSEL IN1+ IN1- IN2+ IN2- IN3+
IN3-
GND
H
H
No. 7106-13/19
VREG
15V
FGIN- 12VREG LVS VCC2 LVSD VREG VREG 12VREG
FGOUT
FGS
VCC3 VM
- FG FILTER
FGIN+
-
+
VREG
+
HP
TOC
VREG VCC1
VCTL
-
+ COMP PRI LOGIC HALL LOGIC TSD DRIVER UL UH VL VH WL WH CURR BR HALL HYS REV SEL AMP LIM RF
LB11823M
(2) MOS transistor drive (lower side PWM) using a 15 V power supply
PWM
PWM OSC
VREF
S/S
SD
PWM IN
OSC
F/R
S/S VCC1 H
PWMIN BR
CSD
F/R
REVSEL IN1+ IN1- IN2+ IN2- IN3+
IN3-
GND
H
H
No. 7106-14/19
Pulse input
LB11823M LB11823M Function Description 1. Output drive circuit This IC employs a direct PWM drive method to minimize the power loss at output. The output TR is normally saturated in the ON condition, adjusting the motor drive power by changing the output on-duty. Output PWM switching is made on UH, VH, and WH output sides. Since UL - WL and UH - WH outputs are of the same output form, either lower PWM or upper PWM can be selected by changing the external output Tr connection method. Selection of diode to be connected to the non-PWM side output requires attention because there is a problem of reverse recovery time. (Unless a diode with the short reverse recovery time is selected, the through current flows in an instant when the PWM side Tr is turned ON.) UL - WL and UH - WH outputs enter the high impedance condition at a time of stop or when the supply voltage is extremely low (below the allowable operation voltage). Accordingly, an appropriate measure (pull-down resistor, etc.) is necessary in the external circuit to prevent an incorrect action due to the leak current. 2. Current limiting circuit The current limiting circuit performs limiting with the current determined from I = VRF/Rf (VRF = 0.5 Vtyp, Rf : current detector resistance) (that is, this circuit limits the peak current). Limiting operation includes decrease in the output on-duty to suppress the current. The current limiting circuit incorporates a filter circuit to prevent an incorrect action of current limiting operation due to detection of the reverse recovery current of output diode during PWM To pin RF operation. This internal filter circuit will be enough to prevent Current detection resistance trouble for normal application. In case of an incorrect action (diode reverse recovery current flowing for 1 s or more), add an external filter circuit (R, C low pass filter, etc.). 3. Power save circuit This IC enters the power save condition to decrease the current dissipation in the stop mode. In this condition, the bias current of most of circuits is cut off. Even in the power save condition, the 5 V regulator output (VREG) is given. If the bias current of Hall device is to be cut, 5V and Hall device may be connected via PNP Tr as a means to meet such needs.
To pin VREG
To pin S/S
Hall device
4. Compatibility with various power supplies To operate this IC with external 5V power supply (4.5 - 5.5 V), short-circuit VCC1 and VREG pin for connection to power supply. To operate this IC with external 12 V power supply (8 - 13.5 V), connect power supply to VCC1 (5 V is generated at the VREG pin to function as a power supply to the control circuit). To operate this IC with external 15 V power supply (13.5 - 19 V), connect power supply to VCC3 and short-circuit 12REG and VCC1 pins (12 V is generated at the 12REG pin to function as a power supply to VCC1). Connect the VCC2 pin basically to the VREG pin. In an application in which the motor rotation speed is to be determined by the external fixed voltage (resistor division, etc.), set VCC2 to 12 V (by connecting to VCC1) to suppress variation of the output duty. (Variation of IC is difficult to affect adversely because of increase in the PWM oscillation amplitude and in the comparator dynamic range.) 5. PWM frequency PWM frequency is determined from the capacity C (F) of capacitor connected to the PWM pin. fPWM . .1/(45000 x C) = Connection of a 1000 pF capacitor causes oscillation of about 22 kHz. Excessively low PWM frequency causes causes a switching sound from the motor while excessively high PWM frequency causes increase in the power loss at the output. About 15 - 50 kHz is recommended. Capacitor GND should be arranged near the IC GND pin as much as possible to protect from the effect of output noise.
No. 7106-15/19
LB11823M 6. Drive method The output duty can be controlled according to any of following methods. * Control with the VCTL pin voltage For the control voltage, refer to the electric characteristics. For control with the VCTL pin, set the PWMIN pin voltage to the L level. * Control with the voltage applied to the TOC pin The TOC pin voltage and PWM oscillation waveform are compared to determine the output duty. The output duty becomes 0 % when the TOC pin voltage exceeds VOH (PWM) (3.0 Vtyp) and 100% when it becomes lower than the VOL (PWM) (1.2 Vtyp). For control with the TOC pin, set the PWMIN pin voltage to the L level. For control with the input level other than the internal CTL amp control input level, external connection of amp allows setting to the arbitrary input level (with the external amp output connected to the TOC pin). For control from the TOC pin, fix the VCTL pin voltage. For an application in which the regulated voltage is applied to the TOC pin through resistor division, etc., it is necessary to take into account the effect of resistor (about 20 k) incorporated between the TOC pin and CTL amp output. (Variation about 20%, temperature characteristics about +0.3%/C). If the noise is included in the voltage to be applied to the TOC pin, chattering may occur in the output. In this case, stabilization with a capacitor is necessary. * Pulse control with the PWMIN pin The output can be controlled on the basis of duty obtained by entering the pulse in the PWMIN pin. The output can be turned ON when the L-level Pin PWMIN input voltage is applied to the PWM pin and OFF when the H-level input voltage is applied. With the PWMIN pin open, the output becomes the H level and is turned OFF. If input with reversed logic is necessary, addition of external Tr (NPN) may be enough. Pulse input For control with the PWMIN pin, set the VCTL pin voltage that is more than the VCTL2 voltage (output duty set to 100%) or connect the TOC pin to GND. 7. Hall input signal The Hall input requires the signal input with an amplitude exceeding the hysteresis width (50 mV max). Considering the effect of noise and phase displacement, the input with the amplitude of 120 mV or more is recommended. When the noise causes disturbance in the output waveform (at a time of phase change) or HP output (Hall signal threephase synthesis output), insert a capacitor to the input to prevent such trouble. The Hall input is used as a signal to determine the input to the restriction protection circuit and the protection circuit during reverse. Though noise is ignored to a certain degree, due attention must be paid when using these protection circuits. When all three phases of Hall input signal are entered, the output is turned OFF entirely (all of UL, VL, WL, UH, VH, and WH OFF). To enter the Hall IC output, fix one side of input (+ or -) to the voltage within the common-mode input range for Hall device. This will allow input from 0 to VCC1 for another single-side input. 8. Circuit for low-voltage protection This circuit detects the voltage applied to the LVS pin. When this voltage drops below the operation voltage (see the electric characteristics), the one-side output (UH, VH, and WH) is turned OFF. To prevent repetition of output ON/OFF near the protection activation voltage, the hysteresis is provided. Accordingly, the output is not recovered unless the voltage rises by about 0.5 V above the activation voltage. The protection activation voltage is for the 5V system detection level. The detection level can be raised by connecting the zenor diode in series to the LVS pin and by shifting the detection level. The LVS pin inrush current at a time of detection is about 65 A. To detection power supply To stabilize rise of the zenor diode voltage, increase the diode current by inserting the resistor between the LVS pin and GND. To pin LVS When the protection circuit is not used, apply a voltage on a level where the protection is not activated, instead of setting the LVS pin open (output OFF with the pin open).
No. 7106-16/19
LB11823M 9. Motor lock protection circuit A motor lock protection circuit is incorporated for protection of IC and motor when the motor is locked. When the Hall input signal is not changed for a certain period with the motor driving, the one-side output (UH, VH, WH) is turned OFF. The time is set by means of a capacity of a capacitor connected to the CSD pin. Set time (s) .= 154 x C (F) . Addition of a 0.01 F capacitor causes a protection time of about 1.54 seconds. (Drive is turned OFF when one cycle of Hall input signal is longer than this time period.) The time to be set must have a sufficient allowance so that the protection is not activated at a normal motor startup. Select the capacitor of 4700 pF or more. The protection circuit is not activated when braking. To cancel the restriction protection condition, one of following steps must be taken: * Stop mode (10 s or more) * Maintaining the output duty 0% condition through input of VCTL or PWMIN for more than the period of tCSD x 2. (tCSD (s) .= 0.5 x C (F). . When the 0.01 F capacitor is added, maintaining for about 10 ms or more is necessary.) * Re-application of power supply The CSD pin acts also as an initial reset pulse generation pin and causes reset of the logic circuit when connected with GND. Accordingly, the motor drive condition can not be obtained. When this pin is not to be used, a resistor of about 150 k and a capacitor of about 4700 pF must be connected to GND in parallel. When the restriction protection circuit is not used, following functions are also invalid: * Protection circuit for the reverse mode * Overheat protection circuit 10. Protection circuit at reverse This circuit becomes effective when the REVSEL pin is set to the L level. When this protection is not necessary, either connect it to the VREG pin or keep it open. When this circuit is effective, all outputs are OFF (all of UL, VL, WL, UH, VH, and WH OFF) when the drive is OFF (output duty 0%). If the condition is switched rapidly from the output drive condition to the drive OFF condition, the current flowing through the motor is returned to the power supply (the coil current flows through output upper and lower diodes to power supply). If this current causes a trouble, such as rise of the supply voltage, etc., it is necessary to reduce the duty in steps, instead of shutting of the drive suddenly. Reverse condition is detected according to the input sequence of Hall signals (IN1, IN2, and IN3). When using this protection circuit, it is necessary to connect the Hall device with motor while considering the Hall input sequence. (See the three-phase logic truth table.) Reversing is judged when the Hall input is reversed by more than 120 degrees in the electrical angle. The drive is not shut OFF immediately after judgment of reverse, but the drive is continued for a certain period (equal to the motor lock protection set time) after drive start. If the reversing condition continues for a certain period (equal to the set time of motor lock protection), the drive is shut OFF (all OFF). When the motor is reversing before it is driven, the drive is continued for a certain period (equal to the set time of motor lock protection). If the motor does not return to forward rotation within this period, the drive is shut OFF (all OFF). To cancel the protection, one of following steps must be taken: * Stop mode (10 s or more) * Maintaining the output duty 0% condition through input of VCTL or PWMIN for more than the period of tCSD x 2. (tCSD(s) .= 0.5 x C (F). When the 0.01 F capacitor is added, maintaining for about 10 ms or more is necessary.) . * Re-application of power supply 11. Overheat protection circuit One-side output (UH, VH,WH) is turned OFF when the junction temperature (Tj) exceeds a specified temperature (TSD). Since the minimum variation of TSD is 125C, thermal design must be made so that Tj = 125C is not exceeded except in the case of abnormality. Accordingly, Pdmax when Tj(max) = 125C is 0.72 W (Ta = 25C). When the motor lock protection is not to be used by inserting in parallel the resistor of about 150k and capacitor of about 4700pF between the CSD pin and GND, this overheat protection circuit does not function. In this case, Tj(max) = 150C, so that Pdmax = 0.9W (Ta = 25C)
No. 7106-17/19
LB11823M 12. Forward/reverse rotation To select forward or reverse in the rotation condition, a measure is taken to prevent flow of the through current (through current due to the output Tr OFF delay time at selection) at the output. Selection during rotation causes the current exceeding the current limit value to flow through the output Tr because of the motor coil resistance and motor reverse electromotive voltage condition. It is therefore necessary to select the external output Tr that is not damaged by this current or to select forward/reverse only when the motor rotation speed has decreased to a certain level. 13. Brake operation Braking is made by setting the BR pin to the L level. Braking consists of a short-circuit brake condition in which all of one-side outputs (UH, VH, or WH) are turned ON while other outputs (UL, VL, WL) are turned OFF. A measure is taken to prevent flow of through current (through current due to output Tr OFF delay time at selection) when the brake is operated or cancelled. While braking is made, current limiting and motor lock protection circuits are not operative. Short-circuit braking causes large current to flow through the output Tr because of motor coil resistance and the motor reverse electromotive voltage condition during operation. It is therefore necessary to select the external output Tr that is not damaged by this current or to activate braking only when the motor rotation speed has decreased to a certain level. 14. Power supply stabilization This IC is of a switching drive type and the power line tends to be affected. It is therefore necessary to connect a capacitor of sufficient capacity for stabilization between the VCC1 pin and GND. To insert a diode in the power line to prevent breakdown through reverse connection of power supply, the power line becomes more readily affected. It is necessary to select a larger capacity. To turn ON/OFF the power supply with a switch, etc., large distance between the switch and capacitor causes substantial deviation of the supply voltage due to the line inductance and inrush current into the capacitor. In certain cases, the withstand voltage may be exceeded. In this case, do not use a ceramic capacitor whose series impedance is low. Instead, use an electrolytic capacitor to suppress the inrush current and to prevent voltage rise. 15. VREG stabilization To stabilize the VREG voltage that is the power supply for the control circuit, connect a 0.1F or more capacitor between VREG and GND. The capacitor GND must be wired near the GND pin of IC as much as possible. 16. FG amplifier Considering connection of the Hall device output, etc., the FG amplifier input does not incorporate the bias voltage. To enter pattern FG, etc., it is necessary to apply the bias voltage to the FGIN+ pin (by applying the VREG/2 voltage determined through division with resistor from VREG, etc.). There are a Schmidt comparator and filter circuit after the FG amplifier output, so that the noise is not readily included in the FGS output. FGOUT and FGS have the same logic.
No. 7106-18/19
LB11823M
Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of August, 2002. Specifications and information herein are subject to change without notice. PS No. 7106-19/19

▲Up To Search▲

Price & Availability of LB11823M

	To Download LB11823M Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .